Conventional structures of transistors which can process multiple logic states are typically formed, as illustrated in FIGS. 1A and 1B, by transistors with multiple threshold voltages (e.g., Vt0, Vt1, and Vt2) and a shared common gate electrode 101. Therefore, an N-state transistor is practically composed of N transistors sharing a common gate (i.e., having a footprint of N transistors). As illustrated in FIG. 1C, the structure of FIGS. 1A and 1B processes four levels of logic signal (or 2 bits), 00, 01, 10, and 11, with the 2-bits of information at input Vg represented by the 2-bits information in the output current (Id). The footprint of each 2 bit logic transistor is actually three times that of a single binary logic transistor, though multi-value logic is much more efficient and faster than current binary logic. Furthermore, the fabrication method to form multi-Vt for each transistor is complicated and costly.
A need therefore exists for methodology enabling formation of multi-value logic transistor structures with a small footprint and the resulting device.